1. Field of the Invention
The present invention relates to a semiconductor device and a method of fabricating the same, and more particularly, it relates to a semiconductor device having a multilayer interconnection structure and a method of fabricating the same.
2. Description of the Background Art
A semiconductor device having a multilayer interconnection structure is well known in the art, as disclosed in "Proceedings of 11th International IEEE VLSI Multilevel Interconnect Conference", Jun. 11-12, 1991 VMIC Conference, p. 146, for example. FIG. 18 is a sectional view showing a conventional semiconductor device having a multilayer interconnection structure, which is disclosed in the aforementioned literature. Referring to FIG. 18, the conventional semiconductor device having a multilayer interconnection structure comprises a silicon semiconductor substrate 101, a first interlayer insulating film 102 having a groove a, which is formed on the silicon semiconductor substrate 101, a first interconnection layer 103 which is formed in the groove a, a second interlayer insulating film 104 having grooves b and c, which is formed on the first interlayer insulating film 102 and the first interconnection layer 103, and a second interconnection layer 105 which is formed in the grooves b and c to be electrically connected with the first interconnection layer 103.
FIGS. 19 to 26 are sectional structural diagrams for illustrating a fabrication process (first to eighth steps) for the conventional semiconductor device having a multilayer interconnection structure shown in FIG. 18. Referring to FIG. 18 and FIGS. 19 to 26, the fabrication process for the conventional semiconductor device having a multilayer interconnection structure is now described.
First, the first interlayer insulating film 102 is formed on the silicon semiconductor substrate 101, as shown in FIG. 19. The silicon semiconductor substrate 101 may alternatively be replaced by an element forming a circuit, such as a transistor or an insulating layer covering such an element, so that the first interlayer insulating film 102 is formed thereon.
Then, the groove a for the first interconnection layer 103 (see FIG. 18) is formed in the first interlayer insulating film 102 by photolithography and etching, as shown in FIG. 20.
Then, the first interconnection layer 103 is formed on the overall surface as shown in FIG. 21, and thereafter etched to expose the surface of the interlayer insulating film 102. Thus, the first interconnection layer 103 is finished in the shape shown in FIG. 22.
Then, the second interlayer insulating film 104 is formed on the overall surface, as shown in FIG. 23.
Then, the groove b for via hole contact is formed by photolithography and etching, as shown in FIG. 24.
Then, the groove c for the second interconnection layer 105 (see FIG. 18) is formed by photolithography and etching, as shown in FIG. 25.
Then, the second interconnection layer 105 is formed on the overall surface as shown in FIG. 26, and thereafter etched to expose the upper surface of the second interlayer insulating film 104. Thus, the second interconnection layer 105 is finished in the shape shown in FIG. 18.
However, the aforementioned conventional semiconductor device having a multilayer interconnection structure has the following problems: When pattern misregistration is caused during formation of the via hole contact groove b and the groove c for the second interconnection layer 105 in the fabrication steps shown in FIGS. 24 and 25, the upper surface of the first interlayer insulating film 102 is disadvantageously recessed by etching. FIG. 27 is a sectional structural diagram for illustrating this problem of the conventional semiconductor device having a multilayer interconnection structure. Referring to FIG. 27, a recess (cavity) d is inevitably formed in the first interlayer insulating film 102 if pattern misregistration is caused during formation of the via hole contact groove b and the groove c for the second interconnection layer 105, as described above. While the etching for forming the grooves b and c is generally stopped by the first interconnection layer 103, such etching undesirably influences the first interlayer insulating film 102 upon occurrence of pattern misregistration, to define the recess d. When such a recess d is defined to reach the underlayer of the first interconnection insulating layer 102, which may be formed by a circuit forming element such as a transistor, for example, a short may be caused across the second interlayer insulating film 102 and the circuit forming element, or the circuit forming element may be damaged.